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Atmel ATWILC1500-MR [PRELIMINARY DATASHEET]
Atmel-42376A-ATWINC1500-MR210P-SmartConnect-Datasheet_102014
5. Host Interfaces
5.1 I
2
C Interface
5.1.1 Overview
Atmel ATWINC1500-MR210P provides an I
2
C bus slave that allows the host processor to read or write any
register in the chip. The ATWINC1500-MR210P supports I
2
C bus Version 2.1 - 2000.
The I
2
C interface, used primarily for control, is a two-wire serial interface consisting of a serial data line (SDA,
Pin 17) and a serial clock (SCL, Pin 18). It responds to the seven bit address value 0x60. The ATWINC1500-
MR210P I
2
C interface can operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data
rates up to 400Kb/s).
The I
2
C is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the SCL
line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform
wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum
capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, please refer to the Philips Specification entitled "The I
2
C -Bus Specification, Version
2.1".
5.1.2 I
2
C Timing
The I
2
C is provided in Figure 5-1 and in Table 5-1 on page 9.
Figure 5-1. ATWINC1500-MR210P I
2
C Timing Diagram
Table 5-1. ATWINC1500-MR210P I
2
C Timing Parameters
Parameter Symbol Min Max Units Remarks
SCL clock frequency f
SCL
0 400 kHz
SCL low pulse width t
WL
1.3 µs
SCL high pulse width t
WH
0.6 µs
W
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