Atmel Wireless LAN Access Point Uživatelský manuál Strana 10

  • Stažení
  • Přidat do mých příruček
  • Tisk
  • Strana
    / 24
  • Tabulka s obsahem
  • KNIHY
  • Hodnocené. / 5. Na základě hodnocení zákazníků
Zobrazit stránku 9
Atmel ATWILC1500-MR [PRELIMINARY DATASHEET]
Atmel-42376A-ATWINC1500-MR210P-SmartConnect-Datasheet_102014
10
5.2 SPI Interface
5.2.1 Overview
Atmel ATWINC1500-MR210P has a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI
interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as shown in Table
5-2. The SPI is a full-duplex slave-synchronous serial interface that is available immediately following reset
when pin 10 (SPI_CFG) is tied to VDDIO.
Table 5-2. ATWINC1500-MR210P SPI Interface Pin Mapping
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted
data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the chip as
well as initiate DMA transfers.
The SPI SSN, MOSI, MISO and SCK pins of the ATWINC1500-MR210P have internal programmable pull-up
resistors (See “Programmable Pull Up Resistors” on page 14). These resistors should be programmed to be
disabled. Otherwise, if any of the SPI pins are driven to a low level while the ATWINC1500-MR210P is in the low
power sleep state, current will flow from the VDDIO supply through the pull-up resistors, increasing the current
consumption of the module.
SCL, SDA fall time t
HL
300 ns
SCL, SDA rise time t
LH
300 ns This is dictated by external components
START setup time t
SUSTA
0.6 µs
START hold time t
HDSTA
0.6 µs
SDA setup Time t
SUDAT
100 ns
SDA hold time t
HDDAT
0 ns Slave and Master default
40 ns Master programming option
STOP setup time t
SUSTO
0.6 µs
Bus free time between STOP and START t
BUF
1.3 µs
Glitch pulse reject t
PR
0 50 ns
Table 5-1. ATWINC1500-MR210P I
2
C Timing Parameters (Continued)
Parameter Symbol Min Max Units Remarks
Pin # SPI Function
10 CFG: Must be tied to VDDIO
16 SSN: Active low slave select
15 MOSI(RXD): Serial Data Receive
18 SCK: Serial Clock
17 MISO(TXD): Serial Data Transmit
Zobrazit stránku 9
1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 23 24

Komentáře k této Příručce

Žádné komentáře