
11
Atmel ATWILC1500-MR [PRELIMINARY DATASHEET]
Atmel-42376A-ATWINC1500-MR210P-SmartConnect-Datasheet_102014
5.2.2 SPI Timing
The SPI timing is provided in Figure 5-2 and in Table 5-3 on page 11
Figure 5-2. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
Table 5-3. SPI Slave Timing Parameters
Parameter Symbol Min Max Units
Clock input frequency f
SCK
48 MHz
Clock low pulse width t
WL
15 ns
Clock high pulse width t
WH
15 ns
Clock rise time t
LH
10 ns
Clock fall time t
HL
10 ns
Input setup time t
ISU
5 ns
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