Atmel AVR AT90S8515-4 Specifikace

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock

10AT90S85150841G–09/01General-purpose Register FileFigure 6 shows the structure of the 32 general-purpose working registers in the CPU.Figure 6. AVR

100AT90S85150841G–09/01Figure 78. Analog Comparator Input Leakage CurrentFigure 79. Watchdog Oscillator Frequency vs. VCC6050403020100-100 0.5 1.51

101AT90S85150841G–09/01Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 80. Pull-up Resistor Current vs. Input Volt

102AT90S85150841G–09/01Figure 82. I/O Pin Sink Current vs. Output VoltageFigure 83. I/O Pin Source Current vs. Output Voltage0102030405060700 0.5 1

103AT90S85150841G–09/01Figure 84. I/O Pin Source Current vs. Output VoltageFigure 85. I/O Pin Input Threshold Voltage vs. VCC01234560 0.5 1 1.5 2 2.

104AT90S85150841G–09/01Figure 86. I/O Pin Input Hysteresis vs. VCCFigure 87. I/O Pin Sink Current vs. Output Voltage00.020.040.060.080.10.120.140.16

105AT90S85150841G–09/01Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addre

106AT90S85150841G–09/01Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add Tw

107AT90S85150841G–09/01DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ← KNone1LD Rd, X Load Ind

108AT90S85150841G–09/01Note: Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed.AT90S8515 Ordering InformationSpeed (MHz) Power Supply Or

109AT90S85150841G–09/01Packaging Information44A1.20(0.047) MAX10.10(0.394) 9.90(0.386)SQ12.25(0.482)11.75(0.462)SQ0.75(0.030)0.45(0.018)0.15(0.006)0.

11AT90S85150841G–09/01In the different addressing modes these address registers have functions as fixed dis-placement, automatic increment and decreme

110AT90S85150841G–09/0144J1.14(0.045) X 45˚PIN NO. 1IDENTIFY0.813(0.032)0.660(0.026)1.27(0.050) TYP12.70(0.500) REF SQ1.14(0.045) X 45˚0.51(0.020)MAX

111AT90S85150841G–09/0140P652.71(2.075)51.94(2.045)PIN113.97(0.550)13.46(0.530)0.38(0.015)MIN0.56(0.022)0.38(0.015)REF15.88(0.625)15.24(0.600)1.65(0.0

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

12AT90S85150841G–09/01SRAM Data Memory – Internal and ExternalFigure 8 shows how the AT90S8515 SRAM memory is organized.Figure 8. SRAM OrganizationTh

13AT90S85150841G–09/01two additional clock cycles is used per byte. This has the following effect: Data transferinstructions take two extra clock cycl

14AT90S85150841G–09/01Register Direct, Two Registers Rd and Rr Figure 10. Direct Register Addressing, Two RegistersOperands are contained in register

15AT90S85150841G–09/01A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specifythe destination or source register.Data

16AT90S85150841G–09/01The X-, Y-, or the Z-register is decremented before the operation. Operand address isthe decremented contents of the X-, Y-, or

17AT90S85150841G–09/01Indirect Program Addressing, IJMP and ICALLFigure 18. Indirect Program Memory AddressingProgram execution continues at address

18AT90S85150841G–09/01Figure 20. The Parallel Instruction Fetches and Instruction ExecutionsFigure 21 shows the internal timing concept for the regis

19AT90S85150841G–09/01I/O Memory The I/O space definition of the AT90S8515 is shown in Table 1.Table 1. AT90S8515 I/O SpaceAddress Hex Name Function$

2AT90S85150841G–09/01Pin Configurations

20AT90S85150841G–09/01Note: Reserved and unused locations are not shown in the table.All AT90S8515 I/Os and peripherals are placed in the I/O space. T

21AT90S85150841G–09/01into T by the BST instruction and a bit in T can be copied into a bit in a register in theregister file by the BLD instruction.•

22AT90S85150841G–09/01Reset and Interrupt HandlingThe AT90S8515 provides 12 different interrupt sources. These interrupts and the sepa-rate reset vect

23AT90S85150841G–09/01$00f ldi r16,low(RAMEND)$010 out SPL,r16$011 <instr> xxx…… ……Reset Sources The AT90S8515 has three sources of reset:• Powe

24AT90S85150841G–09/01The user can select the start-up time according to typical oscillator start-up. The numberof WDT oscillator cycles used for each

25AT90S85150841G–09/01External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longerthan 50 ns will generate a res

26AT90S85150841G–09/01interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to theflag bit position(s) to be cleared.If

27AT90S85150841G–09/01• Bit 6 – INTF0: External Interrupt Flag0When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt

28AT90S85150841G–09/01Timer/Counter Interrupt Flag Register – TIFR• Bit 7 – TOV1: Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow o

29AT90S85150841G–09/01External Interrupts The external interrupts are triggered by the INT1 and INT0 pins. Observe that, ifenabled, the interrupts wil

3AT90S85150841G–09/01Description The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerful inst

30AT90S85150841G–09/01• Bit 5 – SE: Sleep EnableThe SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEPinstruction is execute

31AT90S85150841G–09/01Sleep Modes To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruc-tion must be executed. If an ena

32AT90S85150841G–09/01Timer/Counters The AT90S8515 provides two general-purpose Timer/Counters – one 8-bit T/C and one16-bit T/C. The Timer/Counters h

33AT90S85150841G–09/01Figure 29. Timer/Counter0 Block DiagramTimer/Counter0 Control Register – TCCR0• Bits 7..3 – Res: Reserved BitsThese bits are re

34AT90S85150841G–09/01The Stop condition provides a Timer Enable/Disable function. The CK down dividedmodes are scaled directly from the CK oscillator

35AT90S85150841G–09/01(TCCR1A and TCCR1B). The interrupt enable/disable settings for Timer/Counter1 arefound in the Timer/Counter Interrupt Mask Regis

36AT90S85150841G–09/01Timer/Counter1 Control Register A – TCCR1A• Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0The COM1A1 and COM1A0

37AT90S85150841G–09/01Timer/Counter1 Control Register B – TCCR1B• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)When the ICNC1 bit is cleared (z

38AT90S85150841G–09/01The Stop condition provides a Timer Enable/Disable function. The CK down dividedmodes are scaled directly from the CK oscillator

39AT90S85150841G–09/01Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BLThe output compare registers are 16-bit read/write registers.The Timer

4AT90S85150841G–09/01one clock cycle. The resulting architecture is more code efficient while achievingthroughputs up to ten times faster than convent

40AT90S85150841G–09/01The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If themain program and interrupt routines perform access t

41AT90S85150841G–09/01Figure 32. Effects on Unsynchronized OCR1 LatchingDuring the time between the write and the latch operation, a read from OCR1A

42AT90S85150841G–09/01Watchdog Timer The Watchdog Timer is clocked from a separate On-chip oscillator that runs at 1 MHz.This is the typical value at

43AT90S85150841G–09/011. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to on

44AT90S85150841G–09/01EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the range of 2.5

45AT90S85150841G–09/01• Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to bewritten.

46AT90S85150841G–09/01Prevent EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too low for

47AT90S85150841G–09/01Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween the AT

48AT90S85150841G–09/01Figure 35. SPI Master-slave InterconnectionThe system is single-buffered in the transmit direction and double-buffered in there

49AT90S85150841G–09/01pins are inputs. When SS is driven high, all pins are inputs and the SPI is passive, whichmeans that it will not receive incomin

5AT90S85150841G–09/01current if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the

50AT90S85150841G–09/01• Bit 5 – DORD: Data OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first.When the DORD bit is cle

51AT90S85150841G–09/01SPI Data Register – SPDRThe SPI Data Register is a read/write register used for data transfer between the regis-ter file and the

52AT90S85150841G–09/01UART The AT90S8515 features a full duplex (separate receive and transmit registers) Univer-sal Asynchronous Receiver and Transmi

53AT90S85150841G–09/01If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to theshift register. At this time the UDRE

54AT90S85150841G–09/01The receiver front-end logic samples the signal on the RXD pin at a frequency 16 timesthe baud rate. While the line is idle, one

55AT90S85150841G–09/01UART ControlUART I/O Data Register – UDRThe UDR register is actually two physically separate registers sharing the same I/Oaddre

56AT90S85150841G–09/01The FE bit is cleared when the stop bit of received data is one.• Bit 3 – OR: OverrunThis bit is set if an Overrun condition is

57AT90S85150841G–09/01BAUD Rate Generator The baud rate generator is a frequency divider that generates baud rates according tothe following equation:

58AT90S85150841G–09/01Table 17. UBRR Settings at Various Crystal FrequenciesUART BAUD Rate Register – UBRRThe UBRR register is an 8-bit read/write re

59AT90S85150841G–09/01Analog Comparator The Analog Comparator compares the input values on the positive input PB2 (AIN0) andnegative input PB3 (AIN1).

6AT90S85150841G–09/01Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that canbe configured for use as

60AT90S85150841G–09/01using the SBI or CBI instruction, ACI will be cleared if it has become set before theoperation.• Bit 3 – ACIE: Analog Comparator

61AT90S85150841G–09/01Default, the external SRAM access, is a 3-cycle scheme as depicted in Figure 43. Whenone extra wait state is needed in the acces

62AT90S85150841G–09/01Figure 44. External Data SRAM Memory Cycles with Wait StateSystem Clock ØALEWRRDData/Address [7..0]Data/Address [7..0]Address [

63AT90S85150841G–09/01I/O Ports All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means that the dir

64AT90S85150841G–09/01PORTAn has to be cleared (zero) or the pin has to be configured as an output pin. ThePort A pins are tri-stated when a reset con

65AT90S85150841G–09/01Port B Port B is an 8-bit bi-directional I/O port.Three I/O memory address locations are allocated for the Port B, one each for

66AT90S85150841G–09/01Port B as General Digital I/O All eight pins in Port B have equal functionality when used as digital I/O pins.PBn, general I/O p

67AT90S85150841G–09/01• AIN0 – Port B, Bit 2AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared[zero]) and with the i

68AT90S85150841G–09/01Figure 47. Port B Schematic Diagram (Pins PB2 and PB3)Figure 48. Port B Schematic Diagram (Pin PB4)DATA BUSDDQQRESETRESETCCWDW

69AT90S85150841G–09/01Figure 49. Port B Schematic Diagram (Pin PB5)Figure 50. Port B Schematic Diagram (Pin PB6)DATA BUSDDQQRESETRESETCCWDWPRDMOSPUL

7AT90S85150841G–09/01Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a single

70AT90S85150841G–09/01Figure 51. Port B Schematic Diagram (Pin PB7)Port C Port C is an 8-bit bi-directional I/O port. Three I/O memory address locati

71AT90S85150841G–09/01Port C Data Direction Register – DDRCPort C Input Pins Address – PINCThe Port C Input Pins address (PINC) is not a register; thi

72AT90S85150841G–09/01Port C Schematics Note that all port pins are synchronized. The synchronization latch is, however, notshown in the figure.Figure

73AT90S85150841G–09/01Port D Data Register – PORTDPort D Data Direction Register – DDRDPort D Input Pins Address – PINDThe Port D Input Pins address (

74AT90S85150841G–09/01• INT1 – Port D, Bit 3INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt sourceto the MCU. See th

75AT90S85150841G–09/01Figure 54. Port D Schematic Diagram (Pin PD1)Figure 55. Port D Schematic Diagram (Pins PD2 and PD3)DATA BUSDDQQRESETRESETCCWDW

76AT90S85150841G–09/01Figure 56. Port D Schematic Diagram (Pin PD4)Figure 57. Port D Schematic Diagram (Pin PD5)

77AT90S85150841G–09/01Figure 58. Port D Schematic Diagram (Pin PD6)Figure 59. Port D Schematic Diagram (Pin PD7)

78AT90S85150841G–09/01Memory ProgrammingProgram and Data Memory Lock BitsThe AT90S8515 MCU provides two Lock bits that can be left unprogrammed (“1”)

79AT90S85150841G–09/01the self-timed write operation in the serial programming mode. During programming, thesupply voltage must be in accordance with

8AT90S85150841G–09/01Figure 4. The AT90S8515 AVR RISC ArchitectureA flexible interrupt module has its control registers in the I/O space with an addi

80AT90S85150841G–09/01Enter Programming Mode The following algorithm puts the device in Parallel Programming Mode:1. Apply supply voltage according to

81AT90S85150841G–09/01Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lockbits. The Lock bits are not reset until t

82AT90S85150841G–09/011. Set BS to “1”. This selects high data.2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low

83AT90S85150841G–09/01Figure 62. Programming the Flash Waveforms (Continued)Reading the Flash The algorithm for reading the Flash memory is as follow

84AT90S85150841G–09/01Bit 5 = SPIEN Fuse bitBit 0 = FSTRT Fuse bitBit 7-6, 4-1 = “1”. These bits are reserved and should be left unprogrammed (“1”).3.

85AT90S85150841G–09/01Parallel Programming CharacteristicsFigure 63. Parallel Programming TimingNotes: 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB f

86AT90S85150841G–09/01Serial Downloading Both the program and data memory arrays can be programmed using the SPI bus whileRESET is pulled to GND. The

87AT90S85150841G–09/01ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction

88AT90S85150841G–09/01Figure 65. Serial Programming WaveformsNote: 1. The signature bytes are not readable in lock mode 3, i.e., both Lock bits progr

89AT90S85150841G–09/01Serial Programming CharacteristicsFigure 66. Serial Programming TimingTable 33. Serial Programming Characteristics, TA = -40°C

9AT90S85150841G–09/01Figure 5. Memory Maps$0000Data MemoryProgram Memory32 Gen. PurposeWorking Registers$001F$0020$005F$025F$0060$0260$FFFF64 I/O Reg

90AT90S85150841G–09/01Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°C to +125°C*NOTIC

91AT90S85150841G–09/01Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min” means the lowest value where the

92AT90S85150841G–09/01External Clock Drive WaveformsFigure 67. External ClockNote: See “External Data Memory Timing” for a description of how the dut

93AT90S85150841G–09/01External Data Memory TimingNotes: 1. This assumes 50% clock duty cycle. The half-period is actually the high time of the externa

94AT90S85150841G–09/01Notes: 1. This assumes 50% clock duty cycle. The half-period is actually the high time of the external clock, XTAL1.2. This assu

95AT90S85150841G–09/01Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. All curre

96AT90S85150841G–09/01Figure 70. Active Supply Current vs. VCCFigure 71. Idle Supply Current vs. Frequency024681012142 2.5 3 3.5 4 4.5 5 5.5 6ACTIVE

97AT90S85150841G–09/01Figure 72. Idle Supply Current vs. VCCFigure 73. Power-down Supply Current vs. VCC00.511.522.533.542 2.5 3 3.5 4 4.5 5 5.5 6T

98AT90S85150841G–09/01Figure 74. Power-down Supply Current vs. VCCFigure 75. Analog Comparator Current vs. VCC0204060801001201402 2.5 3 3.5 4 4.5 5

99AT90S85150841G–09/01Analog Comparator offset voltage is measured as absolute offset.Figure 76. Analog Comparator Offset Voltage vs. Common Mode Vol